rev.4.00 jun 05, 2006 page 1 of 8 2sj549(l), 2sj549(s) silicon p channel mos fet rej03g0896-0400 rev.4.00 jun 05, 2006 description high speed power switching features ? low on-resistance r ds (on) = 0.11 ? typ. ? low drive current ? 4 v gate drive devices ? high speed switching outline renesas package code: prss0004ae-a (package name: ldpak (l) ) renesas package code: prss0004ae-b (package name: ldpak (s)-(1) ) 1. gate 2. drain 3. source 4. drain d g s 1 2 3 4 1 2 3 4
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 2 of 8 absolute maximum ratings (ta = 25 c) item symbol value unit drain to source voltage v dss ?60 v gate to source voltage v gss 20 v drain current i d ?12 a drain peak current i d (pulse) note 1 ?48 a body to drain diode reverse drain current i dr ?12 a avalanche current i ap note 3 ?12 a avalanche energy e ar note 3 12 mj channel dissipation pch note 2 50 w channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 1. pw 10 s, duty cycle 1% 2. value at tc = 25 c 3. value at tch = 25 c, rg 50 ? electrical characteristics (ta = 25 c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br) dss ?60 ? ? v i d = ?10 ma, v gs = 0 gate to source breakdown voltage v (br) gss 20 ? ? v i g = 100 a, v ds = 0 zero gate voltage drain current i dss ? ? ?10 a v ds = ?60 v, v gs = 0 gate to source leak current i gss ? ? 10 a v gs = 16 v, v ds = 0 gate to source cutoff voltage v gs (off) ?1.0 ? ?2.0 v i d = ?1 ma, v ds = ?10 v r ds (on) ? 0.11 0.15 ? i d = ?6 a, v gs = ?10 v note 4 static drain to source on state resistance r ds (on) ? 0.16 0.23 ? i d = ?6 a, v gs = ?4 v note 4 forward transfer admittance |y fs | 5 8 ? s i d = ?6 a, v ds = ?10 v note 4 input capacitance ciss ? 580 ? pf output capacitance coss ? 300 ? pf reverse transfer capacitance crss ? 85 ? pf v ds = ?10 v v gs = 0 f = 1 mhz turn-on delay time t d (on) ? 10 ? ns rise time t r ? 55 ? ns turn-off delay time t d (off) ? 85 ? ns fall time t f ? 60 ? ns v gs = ?10 v i d = ?6 a r l = 6 ? body to drain diode forward voltage v df ? ?1.2 ? v i f = ?12 a, v gs = 0 body to drain diode reverse recovery time t rr ? 60 ? ns i f = ?12 a, v gs = 0 di f /dt = 50 a/ s note: 4. pulse test
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 3 of 8 main characteristics channel dissipation pch (w) case temperature tc (c) power vs. temperature derating drain to source voltage v ds (v) drain current i d (a) typical output characteristics gate to source voltage v gs (v) drain current i d (a) typical transfer characteristics ?10 0 ?2 ?4 ?6 ?8 0 ?2?4?6?8 ?10 ?10 0 ?2 ?4 ?6 ?8 0 ?1?2?3?4?5 tc = 75c 80 0 20 40 60 0 50 100 150 200 v ds = ?10 v pulse test ?10 v ?5 v ?4 v ?3.5 v ?2.5 v ?3 v v gs = ?2 v pulse test drain to source voltage v ds (v) drain current i d (a) maximum safe operation area ?10 ?30 ?3 ?0.3 ?1 ?0.1 ?0.1 ?0.3 ?1 ?3 ?10 ?30 ?100 ?100 ta = 25c pw = 10 ms (1 shot) dc operation ( tc = 25c) 1 ms 10 s 100 s operation in this area is limited by r ds (on) gate to source voltage v gs (v) drain to source saturation voltage v ds (on) (v) drain to source saturation voltage vs. gate to source voltage ?1.0 0 ?0.2 ?0.4 ?0.6 ?0.8 0 ?4 ?8 ?12 ?16 ?20 pulse test i d = ?5 a ?2 a ?1 a drain current i d (a) static drain to source on state resistance r ds (on) ( ? ) static drain to source on state resistance vs. drain current 0.2 0.1 0.02 0.05 0.01 ?0.3 ?10 ?30 ?0.1 ?3 ?1 ?100 1 0.5 v gs = ?4 v ?10 v pulse test ?25c 25c
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 4 of 8 0.5 ?40 0 40 80 120 160 case temperature tc (c) 0 0.1 0.2 0.3 0.4 static drain to source on state resistance r ds (on) ( ? ) static drain to source on state resistance vs. temperature pulse test pulse test i d = ?5 a i d = ?12 a forward transfer admittance |y fs | (s) forward transfer admittance vs. drain current drain current i d (a) 20 10 2 5 0.5 1 0.2 ?0.1 ?0.2 ?0.5 ?1 ?5 ?2 ?10 tc = ?25c 75c v ds = ?10 v pulse test 25c reverse drain current i dr (a) reverse recovery time t rr (ns) body-drain diode reverse recovery time ?0.1 ?0.2 ?0.5 ?1 ?2 ?5 ?10 500 200 50 100 20 5 10 di / dt = 50 a / s v gs = 0, ta = 25c 0 ?10 ?20 ?30 ?40 ?50 capacitance c (pf) drain to source voltage v ds (v) typical capacitance vs. drain to source voltage 2000 500 1000 200 20 50 100 10 ciss coss crss v gs = 0 f = 1 mhz 0 0 gate charge qg (nc) drain to source voltage v ds (v) 0 ?20 ?16 ?12 ?8 ?4 ?100 ?80 ?60 ?40 ?20 gate to source voltage v gs (v) dynamic input characteristics 816243240 v ds v gs 1000 100 300 30 3 10 1 ?0.2 ?0.5 ?1 ?5 ?2 ?10 ?0.1 t f t r t d(off) t d(on) drain current i d (a) switching time t (ns) switching characteristics v dd = ?10 v ?25 v ?50 v v dd = ?50 v ?25 v ?10 v ?10 v v gs = ?4 v ?2 a ?5 a ?1 a ?1 a, ?2 a v gs = ?10 v, v dd = ?30 v pw = 5 s, duty 1 %
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 5 of 8 source to drain voltage v sd (v) reverse drain current i dr (a) reverse drain current vs. source to drain voltage 20 25 50 75 100 125 150 0 4 8 12 16 channel temperature tch (c) repetitive avalanche energy e ar (mj) maximum avalanche energy vs. channel temperature derating i ap = ?12 a v dd = ?25 v duty < 0.1 % rg 50 ? ?10 0 ?2 ?4 ?6 ?8 0 ?0.4 ?0.8 ?1.2 ?1.6 ?2.0 pulse test ?5 v v gs = 0, 5 v ?10 v avalanche test circuit avalanche waveform 0 i d v ds i ap v (br)dss v dd e ar = l i ap 2 2 1 v dss v dss ? v dd d.u.t rg i ap monitor v ds monitor v dd 50 ? vin ? 15 v l pulse width pw (s) normalized transient thermal impedance vs. pulse width normalized transient thermal impedance s (t) 3 1 0.3 0.1 0.03 0.01 10 100 1 m 10 m 100 m 1 10 tc = 25c d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot pulse p dm pw t d = pw t ch ? c (t) = s (t) ch ? c ch ? c = 2.5c/w, tc = 25c
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 6 of 8 t r t d(on) vin 90% 90% 10% 10% vout t d(off) 90% 10% t f switching time test circuit waveform vin monitor d.u.t. vin ?10 v r l vout monitor 50 ? v dd = ?30 v
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 7 of 8 package dimensions 10.2 0.3 0.86 0.76 0.1 2.54 0.5 2.54 0.5 + 0.2 ? 0.1 1.3 0.2 4.44 0.2 1.3 0.15 2.49 0.2 0.4 0.1 11.0 0.5 8.6 0.3 10.0 11.3 0.5 + 0.3 ? 0.5 (1.4) 1.37 0.2 previous code prss0004ae-a ldpak(l) / ldpak(l)v mass[typ.] 1.40g ? renesas code jeita package code unit: mm package name ldpak(l) 10.2 0.3 1.37 0.2 (1.5) (1.4) 8.6 0.3 10.0 + 0.3 ? 0.5 4.44 0.2 1.3 0.15 0.1 + 0.2 ? 0.1 0.4 0.1 2.49 0.2 0.86 + 0.2 ? 0.1 2.54 0.5 2.54 0.5 1.3 0.2 3.0 + 0.3 ? 0.5 (1.5) 7.8 6.6 2.2 1.7 7.8 7.0 sc-83 1.30g mass[typ.] ldpak(s)-(1) / ldpak(s)-(1)v prss0004ae-b renesas code jeita package code previous code unit: mm package name ldpak(s)-(1)
2sj549(l), 2sj549(s) rev.4.00 jun 05, 2006 page 8 of 8 ordering information part name quantity shipping container 2SJ549L-e 500 pcs box (sack) 2sj549stl-e 1000 pcs taping note: for some grades, production may be terminated. please contact the renesas sales office to check the state of production before ordering the product.
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 6. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .6.0
|
